Monday, Tuesday, Wednesday and Friday, 12-1PM, EEB 037
Note: There is no class on July 4th
Number systems: positional number system, negative number representation, alphanumeric codes.
Boolean algebra: logic gates, basic theorems of Boolean algebra, minimization by formulas, incompletely specified functions.
Combinational circuit design; integrated circuit characteristics, SSI and MSI circuit design of combinational circuits, encoders, decoders, multiplexers, arithmetic operations.
Sequential logic design using DFFs. Designs include shift registers, counters, and sequential circuits (the design process includes the development and use of state diagrams, state table, state assignment and circuit synthesis).
Programmable logic devices: Field Programmable Gate Arrays (FPGA) and applications of programmable logic devices.
Week 1: Ch1, 2
Week 2: Ch4, 6
Week 3: Ch5.1, 5.3, 5.5-5.8, 3.8, 9.6.1
Week 4: Ch7.1-7.4, 8.1, 10.3
Week 5: Ch8.7 (Midterm review, include all prior reading)
Week 6: Ch7.8, 7.10, 10.1
Week 7: [Design Examples]
Week 8: Ch7.14.2 (Final review, include all prior reading)
Labs (8): 30%
Homework (6): 15%
Midterm (July 21st in class): 20%
Final (August 18th in class): 30%
Random Short Quizes (6): 5%
Dr. Allan Ecker: firstname.lastname@example.org
EEB M358, Office Hours by Appointment (send email w/schedule, or stop by)
Availability best after class.
Chenxin Su: email@example.com
Office hours in student lab Monday through Thursday 1:30-3:30PM in EEB361.
Policies on Collaboration and Cheating
You do not need to follow a particular style guide but being consistent and legible counts! You will be expected to provide comments for your code, to a degree which maximizes legibility. Too few or too many comments are discouraged!
Note: Many labs suggest extra credit up to 120 percent is possible. This class will grade on a 100 percent scale.
Lab 1 Lab due June 30th
Lab 2 Lab due July 7th. Note: please turn in a brief report which shows the schematic you designed and describes its logic function.
Lab 3 Lab due July 14th. Turn in a brief report detailing your design and its schematic.
The Quartus II tutorial, for labs #1 and #2, is here.
The Lab #1 files for Quartus are here.
Most of your labs will involve Verilog. The class Verilog tutorial is here.
There is also a Verilog Quick Reference Card that may be of interest.
Handy Youtube Channel: Ben Eater building a computer from scratch on breadboards is a surprisingly good way to go over nearly everything you need to know in this class! Very useful! (Also I would hold up his wiring choices as a role model for all of you when doing breadboard wiring.)
Labs on student machines:
If you want to use your own machine to do your labs, then grab the Quartus 14.0 files here.
If you are using a laptop, you can bring it to the lab for demos.
If you are using your own desktop machine, or don't want to haul
your laptop to lab, you can FTP your files to the lab machines.
You may want to use Dropbox, Google Docs, or some other cloud storage
account as an intermediate - upload the files from your machine
to your Dropbox (for instance) account, then download the files
to the lab PCs. It is easiest to just send the entire contents
of your lab file, since you'll want the design files,
schematics, project, etc.
IF YOU ARE DOING THIS, TEST IT BEFORE YOUR DEMO TIME.
Notice: You will FAIL a lab if:
-you do not attend your demo
-you do not submit source code
-you tamper with or take another group's parts
-you commit plagurism or otherwise cheat
-you commit any act of gross negligence or disrespect
Homework 1 Due June 30th via Canvas
Homework 2 Due July 7th via Canvas
Homework 3 Due July 14th via Canvas
Two's Compliment Worksheet And Solution (Not graded, you just asked for more problems.)
K-Map Worksheet And Solution (A good thing to be studying!)
Recommended Reading: Memory in SystemVerilog
Final Exam Prep
Final Exam Notes including numerous verilog examples. More to come on Monday including the solution to the practice exam!
Practice Exam (~2 Hours, maybe more) Solution: 1 2