I will start every class (except exams) with a review problem, taken from the following set. I strongly recommend you print these out and bring them to class. BTW, these examples contain many problems that have been on previous exams, so they are good study aids. Doing the problems given at the beginning of class before class starts is a great way to be prepared for the exam.
Here are the eight lab assignments for the quarter, along with their due dates. Labs 1-7 will be due during the week specified, during your demo slot (demo slot signup sheet will be posted in EE361). You should actually do the lab during the previous week. Lab #8 is due by 5pm on the date specified.
Lab 1 Lab start Jan 3, due Jan 10-13
Lab 2 Lab start Jan 10, due Jan 17-20
Lab 3 Lab start Jan 17, due Jan 24-27
Lab 4 Lab start Jan 24, due Jan 31-Feb 3
Lab 5 Lab start Jan 31, due Feb 7-10
Lab 6 Lab start Feb 7, due Feb 14-17
Lab 7 Lab start Feb 14, due Feb 21-24
Lab 8 Lab start Feb 21, due Mar 13, 5pm
The Quartus II tutorial, for labs #1 and #2, is here.
The Lab #1 files for Quartus are here.
Most of your labs will involve Verilog. The class Verilog tutorial is here. There is also a Verilog Quick Reference Card that may be of interest.
If you are using a laptop, you can bring it to the lab for demos. If you are using your own desktop machine, or don't want to haul your laptop to lab, you can FTP your files to the lab machines. You may want to use Dropbox, Google Docs, or some other cloud storage account as an intermediate - upload the files from your machine to your Dropbox (for instance) account, then download the files to the lab PCs. It is easiest to just send the entire contents of your lab file, since you'll want the design files, schematics, project, etc. IF YOU ARE DOING THIS, TEST IT BEFORE YOUR DEMO TIME.
Lab #8 and DE1-SoC Peripherals
Although most lab #8 projects can be done with the base DE1 board, plus
perhaps some extra lights on the breadboard, the DE1-SoC has TONS of
interesting peripherals available. Follow the link on this paragraph's
title to get to a page with tutorials on the DE1-SoC I/Os that are
supported, including System Verilog files to help you use them.
The midterm will be Thursday, February 9.
The final exam will be Thursday, March 16, 8:30-10:20.
The scanned demo time sheet is here.
A sample exam is here.
Questions from the midterm review session are here.
Solutions are here.
The class gradebook is here.