EE 271 Home
Class Email Archive:
Collaboration and Cheating
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James K. Peckol
OFFICE HOURS in EE 137
Welcome to the EE 271 Home
This is the EE 271 home page and it contains a bunch of good stuff
about the class. We will be continually changing things as the quarter progresses and as
new information (especially class announcements and messages) pops in. If you have any
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- Course administration:
- Final Exam TBD: 2:20 p.m. to 4:30 p.m. Wednesday, 10 December 2017
Fundamentals of Digital Logic with VERILOG DESIGN 2nd ed., Brown, Stephen and
Vranesic, Zvonko., McGraw-Hill, 2008.
- Recommended Reading:
- Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, Ciletti,
MIchael D., Prentice Hall, 1999
- The Verilog Hardware Description Language, Thomas, Donald E.
and Moorby, Philip R., Kluwar Academic Publishers, 1996
- Digital Design and Synthesis with Verilog HDL, Sternheim,
E., Singh, R., Trivedi, Y., and Madhavan, R., Automata Publishing Company, 1993
- Verilog HDL A Guide Digital Design and Synthesis, Palnitkar,
Samir, SunSoft Press, A Prentice Hall Title, 1996
These are in pdf format
Get your lecture material here.....
- Verilog Examples:
Get your code here....
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