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EE 271 Home

 

Class Announcements:

Class Email Archive:

Final Projects

 

Office Hours

Finding Us

Policies on Collaboration and Cheating

Class Documentation

Goals and Syllabus

Lecture Schedule

Workload and Grading

Weekly Assignments.

EE 271 Discussion Board

Send e-mail to:


  • Instructor

James K. Peckol

  • TAs

OFFICE HOURS in EE 137

 

 

 



         

hello.gif (1059 bytes)     Welcome to the EE 271 Home Page!                                                                                 

This is the EE 271 home page and it contains a bunch of good stuff about the class. We will be continually changing things as the quarter progresses and as new information (especially class announcements and messages) pops in. If you have any problems with this document or the EE 271 web, in general, send mail to jkp@u.washington.edu.

 


  • Course administration:                                                                                            
  • Meeting Times                                                                                                        
    • Lectures

      More Hall - Room 220 - Cool !!!.... 

      • Monday Tuesday Wednesday and Friday 12:30 p.m. - 1:20 p.m.......WHEW!!!!

       

  • Final Exam TBD: 2:20 p.m. to 4:30 p.m. Wednesday, 10 December 2017
  • Textbook:
    Fundamentals of Digital Logic with VERILOG DESIGN 2nd ed., Brown, Stephen and Vranesic, Zvonko., McGraw-Hill, 2008.
  • Recommended Reading:
    • Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, Ciletti, MIchael D., Prentice Hall, 1999
    • The Verilog Hardware Description Language, Thomas, Donald E. and Moorby, Philip R., Kluwar Academic Publishers, 1996
    • Digital Design and Synthesis with Verilog HDL, Sternheim, E., Singh, R., Trivedi, Y., and Madhavan, R., Automata Publishing Company, 1993
    • Verilog HDL A Guide Digital Design and Synthesis, Palnitkar, Samir, SunSoft Press, A Prentice Hall Title, 1996
  • Lecture Material:


These are in pdf format

Get your lecture material here.....lecture.gif (1365 bytes)

 

  • Verilog Examples:
    Get your code here....

 


Portions of this EE 271 Web  may be reprinted or adapted for academic nonprofit purposes, providing the source is accurately quoted and duly credited. The EE 271 Web: Copyright 2017, Department of Electrical Engineering, University of Washington.

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(Last Update:  09 / 27 / 2017)