EE 469 Home
Class Email Archive:
Final Project Development
Policies on Collaboration and Cheating
Goals and Syllabus
Workload and Grading
James K. Peckol
Welcome to the EE 469
This is the EE 469 home page and it
contains a bunch of good stuff about the class. We will be continually
changing things as the quarter progresses and as new information (especially
class announcements and messages) pops in. If you have any problems with
this document or the EE 469 web, in general, send mail to email@example.com.
Thursday 12:30 p.m. - 2:20 p.m.
- Computer Organization and Design,
Patterson, David A. and Hennessy, John L., Morgan Kaufmann,
- Fundamentals of Digital Logic with VERILOG DESIGN 2nd ed.,
Brown, Stephen and
Vranesic, Zvonko., McGraw-Hill, 2008
- Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL,
MIchael D., Prentice Hall, 1999
- The Verilog Hardware Description Language, Thomas, Donald E.
and Moorby, Philip R., Kluwar Academic Publishers, 1996
- Digital Design and Synthesis with Verilog HDL, Sternheim,
E., Singh, R., Trivedi, Y., and Madhavan, R., Automata Publishing Company, 1993
- Verilog HDL A Guide Digital Design and Synthesis, Palnitkar,
Samir, SunSoft Press, A Prentice Hall Title, 1996
We will also use material provided on the
class and Altera web
These are in Acrobat pdf format
Get your lecture material
Code and Other Examples:
Get your code here....
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